Generally, a clock signal has been used as a reference signal in a clock synchronization system and also has been used to guarantee high-speed operation of the system without an error. When a clock signal from an external circuit is used for system synchronization, a delay time (clock skew) is generated in an internal circuit. To compensate for this clock skew, a clock synchronizing circuits, such as a delay locked loop and a phase locked loop, have been used.
On the other hand, in a DDR SDRAM (Double Data Rate Synchronous DRAM) to perform data input and output operations at rising and falling edges of a high-speed clock signal, it is very important to maintain a duty ratio of 50% for the effective margin of input/output data. Accordingly, a duty cycle correction circuit has been used for generating a clock signal in the constant duty ratio of 50%, irrespective of the duty ratio of the external clock signal, and for compensating for a duty variation of an undesired clock signal.
The duty cycle correction circuit can be classified into an analogue DCC and a digital DCC or into a closed-loop DCC and an open-loop DCC. The analogue DCC is typically implemented by the closed-loop DCC.
FIG. 1 is a schematic diagram illustrating a conventional analogue closed-loop DCC. As shown in FIG. 1, the conventional analogue closed-loop DCC includes a DLL circuit 10 to synchronize a phase of an internal clock signal with that of an external clock signal, a DCC amplifier 12 to amplify an output signal from the DLL 10, and a DCC integrator 14 to receive and integrate DLL clock signals dll_clk from the DCC amplifier 12 and then to provide information about a duty ratio to the DCC amplifier 12.
This analogue closed-loop DCC has merits in that the precision is very high and it is not susceptible to PVT fluctuation; however, it has a shortage in that it takes a lot of time to obtain a desired clock signal of the duty ratio of 50%. Most analogue DCCs have the integrator which stores information in a capacitor (Se Jun Kim et al., “A Low jitter, Fast recoverable, Fully analog DLL using Tracking ADC For High Speed and Low Stand-by power DDR I/O interface”, in Symposium on VLSI Circuits Digest of Technical Papers, 2003). However, in a power-down mode, the information can be lost by a leakage current in the capacitor and therefore lots of time is required to perform a normal operation at the time of restart.
Although the digital DCCs including a DLL can solve the above problem of the analogue DCC by using a digital code, most of the digital DCCs need lots of time until a normal operation is performed after power-up (Tatsuya Matano et al., ‘A 1-Gb/s/pin 512-Mb DDRII SDRAM using a slew-rate-controlled output buffer’ in Symposium on VLSI Circuits Digest of Technical Papers, 2002).